Course Highlights
Dive into Physical Design, where the journey from RTL netlist to final tape-out unfolds, filled with challenges and discoveries. The Google-SkyWater open-source 130nm PDK and Openlane flow are revolutionizing ASIC design, making "an IC for everyone" a closer reality. Join our workshop to master SoC design using this cutting-edge technology.
This course provides:
1. VSD Product-Based Skilling Advantage
a. RISC-V chips and VSDSquadron board built by VSD Student community.
b. Researchers and hobbyists across 153 countries have tested and used it.
c. Get access to 60+ VSD inhouse IPs built by VSD Student community.
2. Chip Tapeout-Oriented Approach using VSD RTL2GDS Flow
a. VSD emphasizes chip tapeout.
b. Focus on real-life scenarios that culminate in tapeout.
c. Offer more practical experience
3. Zero Fees for Tools
a. EDA toolchain is open source.
b. Lifetime access with unlimited licenses,
c. Continue learning and designing even after the program concludes.
4. Career Opportunities
a.Industry recognition for participants who have experience in chip tapeout.
b.Understand how Time-to-market is crucial in this field,
c.Opportunity to work directly on advanced analog, mixed-signal, and RISC-V projects.
5. Cloud-Based Flexibility
a. Self-paced learning
b. Simple login to week's lectures and labs.
c. 24/7 Slack channel with over 150 teaching assistants
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Skill Type
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Domain
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GOI Incentive applicable
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Nasscom Assessment
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Placement Assistance
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Certificate Earned
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Badge Earned
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NOS Details
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Mode of Delivery
Course Details
What will you learn in this Digital VLSI SoC Design and Planning course?
- In this VLSI SoC Design course online, you'll learn the fundamentals and advanced concepts of integrated circuit design. The curriculum guides you through the Place and Route (PnR) process, pivotal in transforming an RTL netlist into a final tape-out ready IC.
- You'll gain hands-on experience in creating and accharacterizing standard cells, such as logic gates and flip-flops, which are the building blocks of digital circuits.
- The course provides a detailed walkthrough of the automated RTL2GDSII process, ensuring you understand how to convert high-level designs into a format ready for silicon fabrication. By engaging with EDA tools, you'll contribute to and benefit from the collective progress in the field.
- This course equips you with the practical skills to plan and execute SoC design projects using the groundbreaking 130nm process node, positioning you at the forefront of modern IC design.
Why should you take this Digital VLSI SoC Design and Planning course?
- VSD offers a unique skilling advantage through its RISC-V chips and VSDSquadron board, widely used by a global community.
- With access to 60+ in-house IPs, VSD emphasizes a practical, chip tapeout-oriented approach in its RTL2GDS Flow, providing real-life design experience.
- The VLSI SoC Design learning path offers zero fees for tools, granting lifetime access to an open-source EDA toolchain, fostering continuous learning.
- It opens doors to significant career opportunities, recognizing participants with chip tapeout experience and offering direct involvement in advanced projects.
- Additionally, VSD provides VLSI SoC Design certification and cloud-based flexibility for self-paced learning, easy access to materials, and robust support through a 24/7 Slack channel, ensuring a comprehensive and accessible educational experience in chip design and tape-out.
Who should take this Digital VLSI SoC Design and Planning course?
- Fresher or recently graduated or experienced professionals looking to brush fundamentals.
- Atleast BE/BTech/ME/MTech or equivalent.
Curriculum
- Introduction to open-source EDA tools and 130nm PDKs
- Floor planning and Standard cell design
- Designing and Characterizing a Library Cell
- Pre-Layout Timing Analysis and Clock Tree Synthesis
- The Final Leap: From RTL2GDS
