RISC-V Based MYTH Foundation Course

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Course Highlights

Master RISC-V & GNU Toolchain – Learn the fundamentals of RISC-V ISA, compiling, debugging, and executing programs.
Explore ABI & Verification – Understand function calls, memory management, and essential verification techniques for hardware design.
Design Digital Logic with TL-Verilog & Makerchip – Build and simulate logic circuits interactively using industry-leading tools.
Construct a Basic RISC-V CPU – Implement a single-cycle microarchitecture, covering registers, ALUs, and instruction execution.
Advance to a Pipelined RISC-V CPU – Optimize CPU performance by handling hazards, control flow, and memory operations.

Designed and simulated a RISC-V processor from instruction fetch to execution.
Gained expertise in microprocessor architecture, pipelining, and hazard handling.
Developed skills in debugging and optimization, essential for VLSI design roles.
Built a strong foundation for careers in semiconductor design, embedded systems, and RISC-V development.
Enhanced their technical portfolio with real-world projects, improving job and research prospects in the VLSI industry.

1 Comprehensive Learning Path
- 1.1 Covers both software and hardware aspects of RISC-V
- 1.2 Learn assembly programming, debugging, and simulation techniques.
- 1.3 Build a functional RISC-V processor from scratch.
2 Hands-on Experience
- 2.1 Work on real-world labs with step-by-step guidance.
- 2.2 Implement register files, ALUs, and instruction decoders.
- 2.3 Simulate and test your own processor design.
3 Industry-Relevant Skills
- 3.1 Gain expertise in microprocessor architecture and design.
- 3.2 Learn pipeline optimization and memory management.
- 3.3 Enhance debugging and performance tuning skills.
4 Engagement with Open-Source Tools
- 4.1 Work with Makerchip, Spike, and RISC-V GCC.
- 4.2 Develop expertise in combinational and sequential logic.
- 4.3 Contribute to open-source processor development.
5 Career & Research Opportunities
- 5.1 Prepares for roles in VLSI, embedded systems, and RISC-V startups.
- 5.2 Builds a strong foundation for higher studies and research.
- 5.3 Gain an edge in technical interviews and hardware competitions.

Undergraduate/graduate students in Electronics, Computer Science, or related fields.
Working professionals looking to transition into RISC-V and processor design.
Hobbyists and researchers interested in open-source hardware development.

Module 1
- Introduction to RISC-V ISA and GNU compiler toolchain
- Introduction to RISC-V basic keywords
- Labwork for RISC-V software toolchain
- Integer number representation
- Signed and unsigned arithmetic operations
Module 2
- Introduction to ABI and basic verification flow
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using iverilog
Module 3
- Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using Makerchip
- Sequential and pipelined logic
- Validity
- Hierarchy
Module 4
- Basic RISC-V CPU micro-architecture
- Microarchitecture and testbench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Module 5
- Complete Pipelined RISC-V CPU micro-architecture/store
- Pipelining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future opportunities

GNU Toolchain (GCC, GDB, Binutils) – Compile, debug, and analyze RISC-V assembly and C programs.
Spike RISC-V Simulator – Simulate and debug RISC-V programs in a virtual environment.
Makerchip & TL-Verilog – Design and simulate digital circuits interactively in the cloud.
Verilator – Perform high-speed simulation of hardware designs for verification.
GTKWave – Visualize and debug waveform outputs from simulations.
RISC-V RTL & Custom CPU Design Frameworks – Implement and test a basic and pipelined RISC-V processor.